Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-03-02
1999-11-02
Phan, Trong Q.
Static information storage and retrieval
Floating gate
Particular biasing
36518511, 36518524, G11C 1606
Patent
active
059782706
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor nonvolatile memory apparatus comprising transistors of which a threshold voltage can be electrically rewritten, or in particular to a semiconductor nonvolatile memory apparatus suitably used for electrically rewriting the threshold voltage frequently and a computer system using such an apparatus, or more in particular to a technical field in which a stable read operation of the semiconductor nonvolatile memory apparatus driven by a single source voltage is possible and the size of a semiconductor nonvolatile memory apparatus driven by a single source voltage can be reduced.
BACKGROUND ART
A semiconductor nonvolatile memory apparatus of a single-transistor-per-cell configuration which can collectively erase the stored information electrically is a flash memory. The flash memory has such a configuration that the area occupied for each bit is small and high integration is possible. For this reason, this memory has been closely watched recently and various research and development efforts are made actively on the structure and the method of driving it.
A first example that has thus far been suggested is a DINOR type described in "Symposium on VLSI Circuits Digest of Technical Papers", pp.97-98, 1993; a second example is a NOR type described in the same papers, pp.99-100, 1993; a third example is an AND type described in the same papers, pp.61-62, 1994; and a fourth example is a HICR type described in "International Electron Devices Meeting Tech. Dig.", pp.19-22.
With each of the above-mentioned types, at the time of the read operation, the word line potential is set to a source voltage Vcc and a low voltage of about 1 V is applied as a bit line potential to prevent weak electrons from being drawn, while information is read from memory cells by a sense amplifier circuit. Let the state in which electrons are stored in a floating gate be defined as an erase mode. In erase mode, the threshold voltage of the memory cell increases. Even if a word line is selected at the time of read operation, therefore, no drain current flows and the bit line potential is held at a precharge potential of 1 V. Let the state in which no electrons are injected (electrons are discharged) be defined as a write mode, on the other hand. In write mode, the threshold voltage value of the memory cell drops. When a word line is selected, therefore, a current begins to flow, and the bit line potential decreases below the precharge potential 1V. The bit line potential is amplified by a sense amplifier thereby to judge a "0" or a "1" state of the information.
A first example so far suggested is an AND type described in "International Electron Devices Meeting Tech. Dig." pp.991-993, 1992, and a second example is a HICR type described in the same papers, pp.19-22, 1993.
In each of these types, the operation of increasing the threshold voltage of a memory cell in the sector representing a unit of each word line is defined as an erase operation.
In the AND type described in "Symposium on VLSI Circuits Digest of Technical Papers", pp.61-62, 1994, a high positive voltage of 16 V is applied to a selected sector, i.e., a selected word line as an erase operation voltage, and the drain and source terminal voltages of the memory cell are set to the ground voltage Vss of 0 V. A voltage difference occurs between the channel and the floating gate of the memory cell in the selected sector, and the electrons in the channel are injected into the floating gate by the Fowler-Nordheim tunnel phenomenon. An erase operation thus is made possible for increasing the threshold voltage of the memory cell.
With the flash memories of the above-mentioned types, a read error is caused when the threshold voltage of the memory cell assumes a negative value. It is therefore necessary to control the threshold voltage of the memory cell not to assume a negative value. For this purpose, the write operation sequence shown in FIG. 29 is executed in the prior art. In the write operation for the AND type constituting
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patent: 5886927 (1999-03-01), Takeuchi
Kobayashi et al., "Memory Array Architecture and Decoding Scheme for 3V Only Sector Erasable DINOR Flash Memory", Symposium on VLSI Circuits Digest of Technical Papers (1993), pp. 97-98.
Umezawa et al., "A New Self-Data-Refresh Scheme for a Sector Erasable 16-Mb Flash EEPROM", Symposium on VLSI Circuits Digest of Tecnical Papers (1993), pp. 99-100.
Takashima et al., "Stand-by/Active Mode Logic for Sub-1 V 1G/4Gb DRAMs", Symposium on VLSI Circuits Digest of Technical Papers (1993), pp. 83-84.
Tanaka et al., "High-Speed Programming and Program Verify Methods . . . ", 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 61-62.
Hisamune et al., "A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories", IEEE meeting technical digest 1993. pp. 2.3.1-2.3.4.
Kato Masataka
Nishimoto Toshiaki
Tanaka Toshihiro
Tsuchiya Osamu
Hitachi , Ltd.
Phan Trong Q.
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