Method of fabricating an interconnection structure for an integr

Details Method of fabricating an interconnection structure for an integr Method of fabricating an interconnection structure for an integr

1993-12-29

1995-08-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437192, 437194, 437228, H01L 2144, H01L 2148

Patent

active

054440220

ABSTRACT:
A novel, high performance, high reliability interconnection structure for an integrated circuit. The interconnection structure of the present invention is formed on a first insulating layer which in turn is formed on a silicon substrate or well. A first multilayer interconnection comprising a first aluminum layer, a first refractory metal layer, and a second aluminum layer is formed on the first insulating layer. A second insulating layer is formed over the first multilayer interconnection. A conductive via is formed through the second insulating layer and into the multilayer interconnection wherein a portion of the via extends above the second insulating layer. A second interconnection is formed on the second insulating layer and on and around the portion of the via extending above the second insulating layer.

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Weide, K. et al., 3-Dimensional Simulations of Temperature and Current Density Distribution in a Via Structure, IEEE/IRPS, pp. 361-365, (Jan. 1992).
Totta, Paul A., Stress Induced Phenomena in Metallizations: U.S. Perspective, American Institute of Physics, pp. 1-20. (1992).
Gardner, D. et al., Layered and Homogenous Films of Aluminum and Aluminum/Silicon with Titanitum, Zirconium, and Tungsten for Multilevel Interconnects, IEDM 84, pp. 114-117 (1984).
Gardner, D. et al., Interconnection and Electromigration Scaling Theory, IEEE Transactions on Electron Devices, vol. ED-34, No. 3, pp. 632-643, (Mar. 1987).

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