Method for manufacturing an integrated circuit having at least o

Details Method for manufacturing an integrated circuit having at least o Method for manufacturing an integrated circuit having at least o

1994-11-01

1995-08-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437 63, 437 89, 437203, 257329, H01L 21265, H01L 21302, H01L 2176, H01L 2120

Patent

active

054439922

ABSTRACT:
An insulating layer is grown on a principal face of a substrate that comprises a source terminal region. A first opening wherein the surface of the source terminal region is partially uncovered is provided in the insulating layer. A vertical layer sequence that comprises at least a channel region and a drain region for the MOS transistor is produced in the first opening by epitaxial growth of semiconductor material within situ doping. A second opening that is at least of a depth corresponding to the sum of the thicknesses of drain region and channel region is produced in the layer structure, a gate dielectric is applied on the surface thereof and a gate-electrode is applied on said gate dielectric.

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H. Grossner et al. "Vertical Si-MOSFETs with Channel Lengths Down to 45 nm", Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, Makuhari, 1993, pp. 422-424.

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