Method for forming electrical isolation in an integrated circuit

Details Method for forming electrical isolation in an integrated circuit Method for forming electrical isolation in an integrated circuit

1993-02-01

1994-12-06

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

H01L 21302

Patent

active

053710355

ABSTRACT:
A layer of silicon-germanium (57) allows electrical isolation structures, having reduced field oxide encroachment, to be formed without adversely effecting the adjacent active regions (64). A high etch selectivity between silicon-germanium and the silicon substrate (52) allows the silicon-germanium layer (57) to be removed, after field oxidation, without damaging the underlying active regions (64).

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