Process for producing memory devices having narrow buried N+ lin

Details Process for producing memory devices having narrow buried N+ lin Process for producing memory devices having narrow buried N+ lin

1994-02-17

1995-05-23

Thomas, Tom

Fishing, trapping, and vermin destroying

437 26, 437 48, H01L 218246

Patent

active

054181763

ABSTRACT:
A process of fabricating a read only memory device (ROM) wherein the buried N+lines have desirable well defined very narrow widths and are closely spaced. In the process, an insulating layer is deposited on the substrate. Openings for the buried N+lines having vertical sidewalls are formed through the insulating layer. Spacer layers are formed on the vertical sidewalls of the openings. Impurities are implanted through the openings. The insulating layers is removed and the substrate is oxidized to form silicon oxide insulation strips over the buried N+implanted regions. Next, the read only memory (ROM) device is completed by fabricating floating gates and overlying control gates between the buried N+lines interconnected by a conductive lines that are orthogonal to the buried N+buried lines.

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patent: 3970486 (1976-07-01), Kooi
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patent: 4385432 (1983-05-01), Kuo et al.
patent: 5025494 (1991-06-01), Gill et al.
patent: 5045489 (1991-09-01), Gill et al.
patent: 5196367 (1993-03-01), Lee et al.

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