Process for flat-cell mask ROM integrated circuit

Details Process for flat-cell mask ROM integrated circuit Process for flat-cell mask ROM integrated circuit

1994-05-06

1995-05-23

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437195, 437984, H01L 218246

Patent

active

054181755

ABSTRACT:
A semiconductor device manufactured by the process including a semiconductor substrate, which comprises the steps of forming buried bit lines below the surface of said semiconductor substrate forming an individual source and drain regions; forming a gate oxide layer on the surface of the substrate; forming a first conductive structure on the gate oxide layer; forming an insulating structure in contact with the first conductive structure; removing material from the surface of the first conductive structure to expose at least a portion of the surface beneath the first conductive structure; and forming on the remaining structure on the semiconductor substrate metal line structures having edges vertically aligned with and above the source and drain regions in the buried bit lines; whereby a compound conductive structure is provided on the semiconductor substrate.

REFERENCES:
patent: 4400865 (1983-08-01), Goth et al.
patent: 4879254 (1989-11-01), Tsuzuki et al.
patent: 5156990 (1992-10-01), Mitchell
patent: 5216270 (1993-06-01), Kaya et al.
patent: 5236853 (1993-08-01), Hsue
patent: 5308777 (1994-05-01), Hong

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