Data processing system for vector processing having a cache inva

Details Data processing system for vector processing having a cache inva Data processing system for vector processing having a cache inva

1984-09-17

1987-01-20

Thomas, James D.

Boots, shoes, and leggings

G06F 1208, G06F 1200, G06F 1300

Patent

active

046384316

ABSTRACT:
A data processing system for vector processing having a main memory accessible in parallel by a plurality of processors, each processor having a cache memory, wherein, in response to a storage instruction given to the main memory by a processor, a main memory block of a given size (BS) and having a give start address (B) and containing element data spaced at an interelement distance (D) being preempted as a result of the storage instruction, a single block address invalidation takes place at each cache memory previously having data stored at that main memory location, the single block address invalidation corresponding to (BS/D) cache address invalidations, whereby repeated sequential individual cache address invalidation operations for each address in the preeempted block no longer are required.

REFERENCES:
patent: 4142234 (1979-02-01), Bean et al.
patent: 4513367 (1985-04-01), Chan et al.
patent: 4525777 (1985-06-01), Webster et al.
Computing Surveys, vol. 14, No. 3, "Cache Memories" by Alan Jay Smith, pp. 473-530, Sep. 1982, Assoc. for Computing Machinery.

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