Boots – shoes – and leggings
Patent
1988-09-02
1990-05-22
Shaw, Gareth D.
Boots, shoes, and leggings
3642434, 36424341, 364243, 3642281, 3642283, G06F 1208, G06F 1516
Patent
active
049282255
ABSTRACT:
A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on the time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache haivng various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occures, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches. A page-mapped I/O cache structure interfaces by a large number of I/O channels which regard a single I/O cache as an exclusive buffer. System operating delays due to maintaining cache coherency, operand cache misses, instruction cache misses, I/O cache misses, and maintaining a cache coherency are substantially reduced.
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Circello Joseph C.
McCarthy Daniel M.
Munguia Gabriel R.
Richardson Nicholas J.
Edgcore Technology, Inc.
Kriess Kevin A.
Shaw Gareth D.
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