Integrated logic circuit with partial scan path circuit and part

Details Integrated logic circuit with partial scan path circuit and part Integrated logic circuit with partial scan path circuit and part

1995-10-03

1997-05-06

Beausoliel, Jr., Robert W.

Excavating

371 221, 371 225, G01R 3128

Patent

active

056278411

ABSTRACT:
Among a plurality of flip-flops coupled with a combinational logic and supplied with a plurality of different clocks, a number of flip-flops are selected so that a respective one of the selected flip-flops is supplied with an associated one of the clocks and has an output thereof connected to one or more of the selected flip-flops, of which at least one is supplied with one of the clocks different from the associated clock of the respective one of the selected flip-flops, and are designed as scan flip-flops to be serially connected to constitute a partial scan path circuit.

REFERENCES:
patent: 5043986 (1991-08-01), Agrawal et al.
patent: 5132974 (1992-07-01), Rosales
patent: 5329533 (1994-07-01), Lin
patent: 5519713 (1996-05-01), Baeg et al.
patent: 5519714 (1996-05-01), Nakamura et al.
T. Kobayashi et al.; "Adapted Flip-Flop Circuit for FLT"; Collected Papers for the 1968 National Meeting of the Association of Electronic and Communications Engineers of Japan, No. 892; p. 962. 1968.

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