Patent
1989-08-10
1990-05-22
James, Andrew J.
357 2311, 357 35, 357 41, 357 42, 357 43, 357 44, 357 49, 357 55, 357 59, H01L 2710, H01L 2702, H01L 2904
Patent
active
049281640
ABSTRACT:
A semiconductor chip circuit device includes cell arrays having pairs of an n-channel device formation region and a p-channel device formation region. Conductive power source lines are selectively formed between the pairs and are situated in grooves in the substrate. The conductive lines are selectively connected to impurity introduction regions in each formation region of each pair. An insulating layer is formed in the grooves over the conductive lines, and wirings selectively connect a plurality of pairs formed on the insulating layer.
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Fujitsu Limited
James Andrew J.
Ngo Ngan Van
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