Central processor utilization monitor

Details Central processor utilization monitor Central processor utilization monitor

1984-02-13

1984-11-27

Zache, Raulfe B.

Boots, shoes, and leggings

364200, G06F 1132, G06F 1134

Patent

active

044854404

ABSTRACT:
Data relative to code instruction use of a central processor unit (CPU) is collected by accumulating counts of code instructions to be executed upon termination of a clock interrupt process over a predetermined interval. Information stored on occurrence of a clock interrupt pulse is evaluated to determine if the code instruction is one under evaluation. If the code instruction is one under evaluation, a count in an associated memory location is incremented. Upon termination of the predetermined interval, the data is read out in histogram form. The data in the histogram is relative to the virtual addresses of the code instructions and, therefore, directly useable by a programmer to evaluate the code use of the CPU without the need for costly and time consuming data unmapping.

REFERENCES:
patent: 3893084 (1975-07-01), Kotok et al.
patent: 4432051 (1984-02-01), Bogaert et al.
patent: 4435759 (1984-03-01), Baum et al.

Affiliated with

Also associated with

Rating

Central processor utilization monitor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Central processor utilization monitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Central processor utilization monitor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2137328