Dynamically selectable polarity latch

Details Dynamically selectable polarity latch Dynamically selectable polarity latch

1984-09-20

1987-01-20

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307272R, 307279, 307443, 307468, H03K 3356

Patent

active

046381830

ABSTRACT:
A selective true or complement storage latch is disclosed which includes a data input switch having an input node connecting to a binary bit input source, a control input for accepting a first or second control state, a first data output node which is selectively connected to the data input node when the control input is in the first state and a second data output node which is selectively connected to the data input node when the control input is in the second state. There is also a first inverting gate having an input connected to the first data output of the data input switch and an output connected to a first storage node. The second inverting gate has an input connected to the first storage node and an output connected to the second storage node, the input of the second inverting gate being connected to the second output of the data input switch, the output of the second inverting gate being connected to the input of the first inverting gate. The data input node is selectively connected to the input of the first inverting gate through the first output of the data input switch when the control input is in a first state and the data input node is selectively connected to the input of the second inverting gate through the second output of the data input switch when the control input is in the second state. In this manner the true value of the data at the data input node is stored in the latch when the control input is in the first state and the complement of the data at the data input node is stored in the latch when the control input is in the second state.

REFERENCES:
patent: 4107556 (1978-08-01), Stewart et al.
patent: 4251739 (1981-02-01), Morozumi
patent: 4380055 (1983-04-01), Larson
patent: 4493077 (1985-01-01), Agrawal et al.
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4506167 (1985-03-01), Little et al.
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4554465 (1985-11-01), Koike
patent: 4554664 (1985-11-01), Schultz
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Reading, Mass., Oct. 1980, pp. 155-156.

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