Method and apparatus for reducing a computational result to the

Details Method and apparatus for reducing a computational result to the Method and apparatus for reducing a computational result to the

1997-06-23

1999-03-23

Shah, Alpesh M.

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39580023, 39580042, 364736, 364737, 364745, 36474503, 364757, G06F 1516

Patent

active

058871810

ABSTRACT:
The method and apparatus for checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. The data signals are represented as unsigned 8-bit binary values. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control with the program having the following operations. The program determines whether the intermediate result signal is in a maximum overflow state or a minimum overflow state. The program sets a first mask signal to have 8 lower bits in an OFF position when the intermediate result signal is in the maximum or minimum overflow state. Otherwise, the program sets the first mask signal to have 8 lower bits in an ON position. Also, the program sets a second mask signal to have 8 lower bits in the OFF position when the intermediate result signal is not in the maximum or minimum overflow state. Otherwise, it sets the second mask signal equal to an upper threshold signal when the data signal is in an overflow state or setting the second mask signal to a lower threshold signal when the data signal is in a minimum overflow state. Finally, the program bitwise ANDs the intermediate result with the first mask signal to obtain a translated data signal, and bitwise ORs the translated data signal with the second mask signal.

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"The UltraSPARC Processor--Technology White Paper; The UltraSPARC Architecture," pp. 1-10, Copyright 1994-1997 Sun Microsystems, Inc., Palo Alto, CA.

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