System for supporting a buffer memory wherein data is stored in

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395306, 395308, G06F 1340

Patent

active

058871489

ABSTRACT:
The present invention provides a memory system interface design, which provides access to a dual width memory bus. Specifically, a subsystem and method provides for interfacing with a 32 bit or a 64 bit bus. The 32 bit bus would be used for low end products, and the 64 bit bus would be used for high end products. A memory control unit (MCU) supports both the 32 bit and 64 bit modes. Selecting a 32 bit or 64 bit memory subsystem gives a user more room to adjust system cost and performance.

REFERENCES:
patent: 4271480 (1981-06-01), Vinot
patent: 4453229 (1984-06-01), Schaire
patent: 4514808 (1985-04-01), Murayama et al.
patent: 4633437 (1986-12-01), Mothersole et al.
patent: 4663728 (1987-05-01), Weatherford et al.
patent: 4667305 (1987-05-01), Dill et al.
patent: 4716527 (1987-12-01), Graciotti
patent: 4766538 (1988-08-01), Miyoshi
patent: 4860198 (1989-08-01), Takenaka
patent: 4878166 (1989-10-01), Johnson et al.
patent: 5045998 (1991-09-01), Begun et al.
patent: 5113369 (1992-05-01), Kinoshita
patent: 5125084 (1992-06-01), Begun et al.
patent: 5148539 (1992-09-01), Enomoto et al.
patent: 5191653 (1993-03-01), Banks et al.
patent: 5202969 (1993-04-01), Sato et al.
patent: 5224213 (1993-06-01), Dieffenderfer et al.
patent: 5235693 (1993-08-01), Chinnaswamy et al.
patent: 5255374 (1993-10-01), Aldereguia et al.
patent: 5255378 (1993-10-01), Crawford et al.
patent: 5265234 (1993-11-01), Ogura et al.
patent: 5274780 (1993-12-01), Nakao
patent: 5280598 (1994-01-01), Osaki et al.
patent: 5440752 (1995-08-01), Lentz et al.
patent: 5611071 (1997-03-01), Martinez, Jr.
patent: 5617546 (1997-04-01), Shih et al.
Zoch et al., "68020 Dynamically Adjusts its Data Transfers to Match Peripheral Ports, " Electronic Design, vol. 33, No. 12, May 1985, pp. 219-225.
Patent Abstracts of Japan, vol. 12, No. 100, (p-683) (2947), Apr. 2, 1988 & JP 62-232061, Oct. 12, 1987.
Patent Abstracts of Japan, vol. 13, No. 175, (P-863) (9561), Apr. 25, 1989 & JP 62-165610, Jul. 2, 1987.

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