CMOS sense amplifier

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

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327 52, 327 54, 327 55, H03F 345

Patent

active

056274840

ABSTRACT:
A memory sense amplifier includes a latch formed for interconnected CMOS gates with an input gate connected to one node of the latch and a reference gate connected to the other node of the latch the reference gate has an input connected to a source of reference voltage and the reference gate and input gate are activated in response to common enable signal. When the input signal, e.g., a data signal from a memory, has a signal value lower than the reference signal value when the two gates are enabled, the reference gate will discharge the node to which it is connected more rapidly than the input gate will discharge the other node. Due to the internal cross connections of the latch, the latch will rapidly change state so as to further discharge the node to which the reference is connected and further charge the other node. In this manner, a rapidly change of state of the latch is accomplished and a binary value output is generated at the latch thereby avoiding the delay which is normally encountered due to the time required for the input signal to achieve a complete change of state.

REFERENCES:
patent: 4274147 (1981-06-01), Padgett et al.
patent: 4386420 (1983-05-01), Ong
patent: 4388705 (1983-06-01), Sheppard
patent: 4645954 (1987-02-01), Schuster
patent: 4804871 (1989-02-01), Walters
patent: 4931675 (1990-06-01), Iwata
patent: 5237533 (1993-08-01), Papaliolios
patent: 5461713 (1995-10-01), Pascucci
IBM Tech. Disc. Bul. vol. 34 No. 10A Mar. 1992 "Combined Sense Amplifier and LSSD Latch" 327/57.

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