Three dimensional processor using transferred thin film circuits

Details Three dimensional processor using transferred thin film circuits Three dimensional processor using transferred thin film circuits

1997-12-08

1999-11-02

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

438 23, 438 26, 438109, 438118, 257700, H02L 2118

Patent

active

059769530

ABSTRACT:
A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.

REFERENCES:
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4649415 (1987-03-01), Hebert
patent: 4727047 (1988-02-01), Bolzer et al.
patent: 4748485 (1988-05-01), Vasudev
patent: 4818728 (1989-04-01), Rai et al.
patent: 4847146 (1989-07-01), Yeh et al.
patent: 4897708 (1990-01-01), Clements
patent: 4980034 (1990-12-01), Volfson et al.
patent: 5128737 (1992-07-01), van der Have
patent: 5138437 (1992-08-01), Kumamoto et al.
patent: 5202754 (1993-04-01), Bertin et al.
patent: 5212778 (1993-05-01), Dally et al.
patent: 5256562 (1993-10-01), Vu et al.
patent: 5258325 (1993-11-01), Spitzer et al.
patent: 5280192 (1994-01-01), Kryzaniwsky
patent: 5324980 (1994-06-01), Kusunoki
patent: 5347154 (1994-09-01), Takahashi et al.
patent: 5354695 (1994-10-01), Leedy
patent: 5373189 (1994-12-01), Massit et al.
patent: 5376561 (1994-12-01), Vu et al.
patent: 5407511 (1995-04-01), Nakatani et al.
patent: 5656548 (1997-08-01), Zavracky et al.
Yamazaki, et al., "4-Layer 3-D IC Technoligies For Parallel Signal Processing" IDEM pp. 599-602 (1990).
Kopin Corp., "3D Circuits Formed By Film Transfer Techniques" DARPA BAA 92-18 Proposal pp. 1-50 (Jul. 31, 1992).
Nishimura, et al., "Three Dimensional IC For High Performance Image Signal Processor" IEDM pp. 111-114 (1987).
Sasaki, "Feasibility of 3D Integration" ETT 1 (2) :55-60 (Mar./Apr. 1990).
Gotzlich, "Technology and Devices From Silicon Based Three-Dimensional Circuits" pp. 1-35 (1989).
Neudeck, "Three-Dimensional CMOS Integration" Circuits and Devices pp. 32-38 (Sep. 1990).
Hayashi, et al., "A New Three Dimensional IC Fabrication Technology, Stacking Thin Film Dual-CMOS Layers" IEDM pp. 657-660 (1990).
"Industry News" Micro-conductor Int'l one page (Dec. 1991).
Kawasura, et al., "3-D High-Voltage CMOS ICS By Recystallized SOI Merged With Bulk Control-Unit" IEDM pp. 758-761 (1987).
Dunne, et al., "Material and Devices Toward Three-Dimensional Integration" Microelec. Eng. 8 (1988) pp. 235-253.
Ulf Kong, "Draft Designs For Multi-functional IC's Three Dimensional Integration" Elektroniker No. Oct. 1989; pp. 79-82 (with translation).
Ernst Hofmeister, "Microelectronics 2000" TRENDS (1989); pp. 1-16 (with translation).
R.W. Johnson, et al., "Multi-chip Modules--Systems Advantages, Major Constructions, and Materials Technologies," IEEE Press, The Institute of Electrical and Electronics Engineers, Inc., pp. 150-155 (1991).

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