Methods and apparatus for error correction

Details Methods and apparatus for error correction Methods and apparatus for error correction

1997-06-26

1999-03-23

Baker, Stephen M.

Excavating

H03M 1300

Patent

active

058870059

ABSTRACT:
An error correction decoder which includes a syndrome calculator, an error locator polynomial calculator, a standard error locator polynomial calculator, an error transform calculator and an inverse error transform calculator. These error correction decoder calculators provide a pipelined architecture for performing Reed-Solomon error correction calculations quickly. In the inverse error transform calculator, a method for calculating inverse error transforms is used. The method is adapted to receive error transforms in the same sequence as the error transforms are output by the error transform calculator without the need for buffering between the error transform calculator and the inverse error transform calculator and without the addition of substantial timing delays. In particular, the inverse error transform calculator is adapted to receive error transforms in the sequence E.sub.0, E.sub.1 . . . E.sub.N-1. The inverse error transform calculator is adapted to calculate inverse error transforms using the equation ##EQU1## In one embodiment, the inverse error transform calculator implements the method using a semiconductor device having adders, multipliers, memory elements and a recursive feedback loop to implement this equation. The inverse error transform calculator may use a plurality of cells to calculate a plurality of inverse error transforms.

REFERENCES:
patent: 4868828 (1989-09-01), Shao et al.
patent: 5323402 (1994-06-01), Vaccaro et al.
Shao et al., "A VLSI Design of a Pipeline Reed-Solomon Decoder", IEEE Transactions on Computers, vol. C-34, No. 5, May 1985, pp. 393-403.

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