Semiconductor memory device allowing reduction in power consumpt

Details Semiconductor memory device allowing reduction in power consumpt Semiconductor memory device allowing reduction in power consumpt

1997-04-07

1999-03-23

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

36523006, 365194, G11C 800

Patent

active

058869468

ABSTRACT:
A synchronous signal generating circuit 100 includes a delay circuit 110 which receives and delays an external clock signal Ext.CLK by a predetermined time for issuing the same, a phase comparator 120 which compares an output of the delay circuit 110 with a phase of the external clock signal Ext.CLK, a variable constant current source circuit 140 which varies in a digital manner a value of a constant current supplied to an output node 140a based on a result of comparison by the phase comparator 120, and a delay control circuit 150 which adjusts a degree of delay by the delay circuit 110 in accordance with the value of the constant current supplied to the output node 140a. The degree of delay by the delay circuit 110 is controlled in accordance with the value of the constant current which varies linearly in accordance with the result of phase comparison.

REFERENCES:
patent: 5455803 (1995-10-01), Kodama
patent: 5581512 (1996-12-01), Kitamura
patent: 5602798 (1997-02-01), Sato et al.
patent: 5629897 (1997-05-01), Iwamoto et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device allowing reduction in power consumpt does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device allowing reduction in power consumpt, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device allowing reduction in power consumpt will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2132992