Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-07-09
1999-03-23
Mai, Son
Static information storage and retrieval
Floating gate
Particular biasing
3651852, 36518524, G11C 1606
Patent
active
058869271
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a nonvolatile memory device and, more particularly a nonvolatile memory device which has verify function and which comprises memory cells for verification (hereinafter referred to as "verify cells") in addition to a plurality of memory cells connected to word lines.
BACKGROUND ART
With a nonvolatile memory device such as an EEPROM or a flash memory, it must be confirmed whether data has been correctly written into the memory device after the data-writing operation or has been erased therefrom after the data-erasing operation. This confirmation step shall be called "verification." Hitherto, verification has been performed, first by reading data items from the memory cells (i.e., array cells) of a nonvolatile memory device, one by one, and then by comparing each data item with the contents of the memory cell transistor (i.e., reference cell transistor).
In a nonvolatile memory device such as an EEPROM or a flash memory, for example, data is written or erased for a prescribed time, and then it is determined whether or not the data has been correctly written or erased. If NO, the data is written or erased repeatedly, each time for the prescribed time, until it is confirmed that the data has been correctly written or erased.
This method of verification is to read the data items from the memory cells (i.e., array cells) of the nonvolatile memory device, one by one, and then by comparing each data item with the contents of the memory cell transistor (i.e., reference cell transistor), after the data is actually written into or erased from the memory cells.
Recently the integration density of memories has increased, and the number of memory cells incorporated in each memory has increased. It therefore takes much time and labor to examine the threshold values of the memory cells, one by one.
U.S. Pat. No. 5,142,496, for example, discloses the technique of conducting verification. In this technique, a reference column is provided at an end of the cell matrix, the sense ratio set in a sense circuit is adjusted, and the outputs from the array cells are compared with the output of the reference cell connected to the same word line as the array cells.
Since one reference cell is connected to each word line, the characteristic of any array cell connected to the same word line can be determined when the reference cell is verified.
In the invention of U.S. Pat. No. 5,142,496, a sense amplifier compares the outputs from the array cells with the output of the reference cell connected to the same word line. To verify the array cells it is necessary to select the array cells which have been selected to write data items, and to compare the contents of the array cells with those of the reference cell. Even if data is written, for example, in page mode and thus in unit of a word line, at least the contents of the array cells selected must be compared with those of the reference cell. It would take time to select one or more of the memory cells. Much time is inevitably required to perform verification.
Further, the reference cells connected to the word lines, one to each word line, differ in characteristic, which is inevitable due to the manufacturing process. Consequently, the verification standard between the reference cells must be changed for each word line.
As described above, with the conventional nonvolatile memory device it is necessary to verify all memory cells selected to confirm that data has been correctly written into or erased from the memory cells incorporated in the array. The verification requires much time and labor.
DISCLOSURE OF INVENTION
Accordingly it is the object of the present invention to provide a nonvolatile memory device with verify function, in which verification can be conducted fast and accurately, thereby to write and erase data with ease and at high speed.
A nonvolatile memory device with verify function, according to the invention, comprises a plurality of word lines arranged in row direction; a plurality of bit lines arranged in column dire
REFERENCES:
patent: 5408432 (1995-04-01), Watanabe
patent: 5629892 (1997-05-01), Tang
patent: 5671180 (1997-09-01), Higuchi
patent: 5675536 (1997-10-01), Sim
Mai Son
NKK Corporation
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