Latch optimization in hardware logic emulation systems

Details Latch optimization in hardware logic emulation systems Latch optimization in hardware logic emulation systems

1996-09-23

1999-03-23

Teska, Kevin J.

Boots, shoes, and leggings

G06F 9455, G06F 1750

Patent

active

058869042

ABSTRACT:
A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clock signal. If consecutive latches are clocked by the same clock signal, for example, the same phase of the same master clock, a transparency condition exists. Transparent latches are transformed into either a flip-flop/buffer/multiplexer circuit or a buffer circuit depending upon whether the latch in the logic design has an enable input. If consecutive latches in a design are clocked by different clock signals, i.e., different phases of the master clock, no transparency condition exists. Non-transparent latches are transformed into a flip-flop.

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