Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1997-07-14
1999-03-23
Saadat, Mahshid
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257751, 257752, 257758, 257763, 257773, H01L 2348, H01L 2352, H01L 2940
Patent
active
058864113
ABSTRACT:
Trenches are formed in a silicon oxide film, a barrier metal film and tungsten film are formed, and the surface portion is polished to make the surface flat and form interconnection layers of the tungsten film in the trenches. Then, the tungsten film and barrier film are etched to form a stepped portions, a silicon nitride film is formed to fill the stepped portions, and the silicon nitride film is polished to make the surface flat. After this, the silicon oxide film is etched by use of a mask pattern to form contact holes in a self-aligned manner. Then, a silicon nitride film is formed and the surface portions is etched back to form side walls on the side walls of the contact holes and a barrier metal film and tungsten film are sequentially formed to fill the contact holes, then the tungsten film and barrier metal film are polished until the silicon oxide film and silicon nitride film are exposed, and as a result, the surface is made flat.
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patent: 5705838 (1998-01-01), Jost et al.
patent: 5708303 (1998-01-01), Jeng
Carter W. Kaanta et al., "Dual Damascene: A ULSI Wiring Technology", VMIC Conference, pp. 144-152, Jun. 11-12, 1991.
D. Kenney et al., "A Buried-Plate Cell for a 64-Mb Dram", Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15, Dec. 1992.
M. Fukumoto et al., "Stacked capacitor cell technology for 16M DRAM using double self-aligned contacts", ESSDERC 90, Nottingham, Session 6A2, pp. 461-464, Sep. 1990.
Kabushiki Kaisha Toshiba
Saadat Mahshid
Wilson Allan R.
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