Process for fabricating semiconductor integrated circuit device

Details Process for fabricating semiconductor integrated circuit device Process for fabricating semiconductor integrated circuit device

1985-03-18

1987-01-20

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 148187, H01L 2138

Patent

active

046371249

ABSTRACT:
Herein disclosed is a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers formed simultaneously at both the sides of a gate electrode thereof. The P-channel MISFET has its source and drain regions formed by a boron ion implantation using the gate electrode and the paired side wall spacers as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode.

REFERENCES:
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4488351 (1984-12-01), Momose
patent: 4505024 (1985-03-01), Kawate et al.
patent: 4525920 (1985-07-01), Jacobs et al.
patent: 4530150 (1985-07-01), Shirato
patent: 4536944 (1985-08-01), Bracco et al.
Yamaguchi et al., IEDM, Wn.D.C., Dec. 5-7, 1983, pp. 522-525.
Tsang et al., IEEE Trans. on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 590-596.

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