Excavating
Patent
1987-12-28
1989-12-12
Fleming, Michael R.
Excavating
371 224, G06F 1100
Patent
active
048872679
ABSTRACT:
A logic integrated circuit includes a FIFO type memory circuit provided for testing. A logic value at each test node is stored in the memory circuits during a write-in enable period set by a control signal from a flip-flop or an externally supplied control signal, and the memory data is read out from the memory circuits, to trace the output states of internal bus, register, multiplier, and the like.
REFERENCES:
patent: 4194113 (1980-03-01), Fulks
patent: 4510572 (1985-04-01), Reece
patent: 4779042 (1988-10-01), Ugenti
patent: 4788492 (1988-11-01), Schubert
Eichelberger et al., "A Logic Design Structure for LSI Testability," Proc. Design Automation Workshop 14th, pp. 462-468, ('77).
Fleming Michael R.
Kabushiki Kaisha Toshiba
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