Processing circuit with asymmetry corrector and convolutional en

Details Processing circuit with asymmetry corrector and convolutional en Processing circuit with asymmetry corrector and convolutional en

1984-09-11

1987-07-21

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

371 43, 375 54, 375 76, 375120, H04L 2740, G06F 1110

Patent

active

046823433

ABSTRACT:
A processing circuit (P) is provided for correcting for input parameter variations, such as data and clock signal asymmetry, phase offset and jitter, noise and signal amplitude, in incoming data signals. An asymmetry corrector circuit (C) performs the correcting function and furnishes the corrected data signals to a convolutional encoder circuit (E). The corrector circuit (C) further forms a regenerated clock signal from clock pulses in the incoming data signals and another clock signal at a multiple of the incoming clock signal. These clock signals are furnished to the encoder circuit (E) so that encoded data may be furnished to a modulator (M) at a high data rate for transmission.

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NASA Tech Briefs, vol. 7, No. 4, Summer 1983, pp. 378-379, "NRZ Data Asymmetry Correction and Convolutional Encoder" and NASA Technical Support Package, vol. 7, No. 4, Summer 1983, MSC-20187 (same title).

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