Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Patent
1998-01-15
1999-03-23
Graybill, David
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
438519, 438611, 438669, 438680, 438685, 438686, 438688, 438694, 438763, 438780, H01L 21283, H01L 21306, H01L 21311, H01L 21316
Patent
active
058858571
ABSTRACT:
A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.
REFERENCES:
patent: 5117280 (1992-05-01), Adachi
patent: 5217917 (1993-06-01), Takahashi et al.
patent: 5488007 (1996-01-01), Kim et al.
patent: 5747380 (1998-05-01), Yu et al.
patent: 5763057 (1998-06-01), Sawada et al.
Inoue Yushi
Naito Masaru
Yamaha Takahisa
Graybill David
Yamaha Corporation
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