Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Patent
1993-11-10
1999-03-23
Graybill, David E.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
438127, 438128, H01L 2156, H01L 2160, H01L 2170
Patent
active
058858504
DESCRIPTION:
BRIEF SUMMARY
An object of the present invention is a method for the interconnection of stacked packages as well as the device resulting therefrom, each of the packages encapsulating an electronic component such as a semiconductor chip, containing for example an integrated circuit, or an electronic circuit or a sensor; these components shall hereinafter be designated by the terms components or chips without discrimination.
The making of present-day electronic systems, for both civilian and military use, should take account of increasingly greater requirements of compactness owing to the constantly rising number of circuits that are being implemented. In this context, it has already been proposed to make stacks of integrated circuits as described, for example, in the U.S. Pat. No. 4,706,166. According to this patent, the chips themselves are positioned on a printed circuit, placed against one another perpendicularly to the printed circuit; the connection pads of each of the chips are brought to one and the same side of the chip; this side is positioned on the printed circuit, and the connections with the printed circuit are made thereon. However, this arrangement has limitations, related notably to the number of pads that it is physically possible to place on only one side of a semiconductor chip; in addition, this arrangement is costly because the chips are not standard ones (the arrangement of the pads has to be modified); finally, there is little access possible to the connections thus made and these connections, in addition, cannot be seen, whereas in certain applications they need to be seen. This drawback limits their use.
An object of the present invention is to circumvent the preceding limitations by the stacking and interconnecting no longer of chips but of packages containing the components and by using the faces of the stack as interconnection surfaces.
Thus, firstly, the above drawbacks and limitations are avoided and, secondly, the cost price of the components is reduced. For, especially when the components are semiconductor chips, there are chips in packages, generally made of plastic, that are available in the market at prices below those of the chips alone, chiefly because of the quantities manufactured. Furthermore, they are easier to test and hence cost less.
More specifically, an object of the invention is a method of interconnection as defined by claim 1, as well as a device comprising stacked and interconnected packages as defined by claim 6.
Other objects, special features and results of the invention shall emerge from the following description, illustrated by the appended drawings, of which:
FIG. 1 represents a mode of carrying out the method according to the invention;
FIGS. 2a and 2b show examples of packages capable of being inserted into the device according to the invention;
FIG. 3 shows a step for the manufacture of the device according to the invention;
FIGS. 4a to 4c show different variants of a following step in the manufacture of the device according to the invention;
FIG. 5 shows a partial view of an embodiment of the device according to the invention;
FIGS. 6a and 6b show details of the embodiment of the previous figure;
FIG. 7 shows another embodiment of the device according to the invention.
FIG. 8 shows an alternative mode of carrying out the method according to the invention;
FIG. 9 shows a step of the manufacturing method according to the previous figure.
In these different figures, the same references refer to the same elements. Furthermore, for the clarity of the drawings, the figures have not been drawn to true scale.
FIG. 1 therefore illustrates a mode of carrying out the method according to the invention.
The first step of the method, referenced 11, consists in stacking packages, each containing an electronic component, for example a semiconductor chip in which an integrated circuit is made. Each of the packages is furthermore provided with connection pins.
FIG. 2a illustrates an example of a package such as this.
This figure shows a package, with the general reference 2, that
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Val, Christian: 3-D Interconnection for Ultra-Dense Multichip Modules, 1990, pp. 814-821.
"Thomson-CSF"
Graybill David E.
Plottel Roland
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