Programmable logic array with 2-bit input partitioning

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307448, 307449, 307468, H03K 19177

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active

048869872

ABSTRACT:
A programmable logic array comprises an input decoder having a plurality of paired first transistors inputting signals and connected in series to each other, the input decoder outputting predetermined logic signals through the first transistors based on the input signals and inverted input signals thereof; second transistors for supplying the logic output signals of the input decoder to corresponding input lines in an AND array region; and third transistors for predischarging the input lines of the AND array region.

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patent: 4739195 (1988-04-01), Masaki
Moore et al., "Metal Oxide Transistor Decode Circuit", IBM T.D.B., vol. 9, No. 6, Nov. 1966, pp. 703-704.
Cases et al., "Improving the Performance of a Transfer Gate PLA Structure", IBM T.D.B., vol. 25, No. 4, Sep. 1986, pp. 2215-2216.
Fleisher et al., "An Introduction to Array Logic", IBM Journal of Research and Development, Mar. 1975, pp. 98-109.

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