Computer method/apparatus for performing a basic input/output sy

Details Computer method/apparatus for performing a basic input/output sy Computer method/apparatus for performing a basic input/output sy

1996-07-03

1997-12-30

Beausoliel, Jr., Robert W.

G06F 1300

Patent

active

057040354

ABSTRACT:
A method and apparatus in a personal computer for performing a basic input/output system (BIOS) power on system test (POST) that uses three data patterns. The first data pattern (plus Inverse pattern) is used to test data bit integrity. the second data pattern (plus inverse pattern) encoded by address is used to test address line integrity. The third pattern is a pattern where all bits are null. Each pattern is 64 bits wide (a 32 bit data pattern plus 32 bit inverse data pattern). The test uses the Processor or Main Memory Controller's Byte Enables to speed the execution of the test. This is optimized for both 32 and 64 bit data paths. The invention has the advantage that it uses a 64 Bit data test, finds Data Bit and Address Line failures, tests boundary conditions rather than every data point, and results in very fast execution.

REFERENCES:
patent: 5006787 (1991-04-01), Katirciogula
patent: 5051997 (1991-09-01), Sakashita
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5471482 (1995-11-01), Byers et al.

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