Excavating
Patent
1986-03-03
1987-10-06
Fleming, Michael R.
Excavating
365203, G06F 1100
Patent
active
046988122
ABSTRACT:
An error-correcting memory system includes a storage module which receives an address and which reads data bits and check bits at the address, and it further includes a zero DC power gate array which corrects errors in the data bits by decoding multiple minterms from the check bits; wherein the gate array is comprised of: a plurality of capacitors, one for each of the minterms; a control circuit for generating a control signal that is in one state when the minterms are to be detected and is otherwise in an opposite state; a charging circuit, coupled between the control circuit and the capacitors, for charging all of the capacitors only when the control signal is in its opposite state; and a discharging circuit, coupled between the control circuit and the capacitors, for indicating the presence of the minterms by selectively discharging the capacitors as a selectable decode of the check bits only when the control signal is in its one state.
REFERENCES:
patent: 3893070 (1975-07-01), Bossen
patent: 4535455 (1985-08-01), Peterson
patent: 4578776 (1986-03-01), Takemae
patent: 4641310 (1987-02-01), Martens
patent: 4646303 (1987-02-01), Narusawa
patent: 4646304 (1987-02-01), Fossati
Fassbender Charles J.
Fleming Michael R.
Marhoefer L. Joseph
Unisys Corporation
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