RAM memory overlay gate array circuit

Details RAM memory overlay gate array circuit RAM memory overlay gate array circuit

1985-10-18

1987-10-06

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1308

Patent

active

046987495

ABSTRACT:
This circuitry expands the memory addressing arrange of a microprocessor beyond its directly addressable memory capacity. This circuit uses the status outputs of the microprocessor to segregate memory accesses for program code instructions from accesses for other data. This segregation scheme assigns different memory banks to program code instructions and to data. Memory reads and writes for scratch pad data are performed from one bank of memory. Memory reads for program code instructions are performed from a separate memory bank. This memory bank technique can double the size of a microprocessor's directly addressable memory without changing the microprocessor's architecture. This circuitry is suitable for implementation with CMOS gate array technology.

REFERENCES:
patent: 4080651 (1978-03-01), Cronshaw
patent: 4126893 (1978-11-01), Cronshaw et al.
patent: 4158227 (1979-06-01), Baxter et al.
patent: 4340932 (1982-07-01), Bakula et al.
patent: 4393443 (1983-07-01), Lewis
patent: 4410941 (1983-10-01), Barrow et al.
patent: 4473877 (1984-09-01), Tulk

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