Patent
1986-05-16
1987-10-06
Carroll, J.
357 231, 357 237, 357 59, 357 67, 357 71, H01L 2978, H01L 2702, H01L 2904, H01L 2348
Patent
active
046986596
ABSTRACT:
An MOS transistor of second conductivity type is provided which is formed in a semiconductor substrate of first conductivity type and includes a first source region of second conductivity type, a first drain region of second conductivity type, and a gate electrode provided on a gate insulation layer. Further, an MOS transistor of first conductivity type is provided which is stacked on the MOS transistor of second conductivity type and includes a second source region, a second drain region and the gate electrode. The first and second source regions are connected to each other through a conductive layer which is selected from a given metal layer and a given metal silicide layer.
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Colinge et al., "A High Density CMOS Inverter With Stacked Transistors," IEEE Electron Device Letters, vol. EDL-2, No. 10, Oct. 1981; New York, pp. 250-251 (FIG. 1).
J. F. Gibbons et al., "One-Gate-Wide CMOS Inverter on Laser-Recrystallized Polysilicon" IEEE Electron Device Letters, vol. EDL-1, (1980) pp. 117-118.
Colinge et al., "Stacked Transistors CMOS (ST-MOS), an NMOS Technology Modified to CMOS," IEEE Journal of Solid-State Circuits, vol. SC-17, No. 2, Apr. 1982.
Carroll J.
Tokyo Shibaura Denki Kabushiki Kaisha
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