Transparent shift register latch for isolating peripheral ports

Details Transparent shift register latch for isolating peripheral ports Transparent shift register latch for isolating peripheral ports

1985-10-23

1987-10-06

Karlsen, Ernest F.

Electricity: measuring and testing

Plural, automatically sequential tests

324158R, 371 25, G01R 3128, G06F 1100

Patent

active

046985883

ABSTRACT:
A transparent shift register latch (170) includes a normal operating gate (182) and a test gate (184) for selectively connecting data to a node (180). The node (180) is input to an isolation gate (186) through an inverter (188) for connection to an output node (190). A peripheral port (172) is interfaced with the output node (190) through an isolation gate (192). The gates (186) and (192) are operable in a test mode to interface data stored on the node (180) with the output of the latch (170) and inhibit input of data from the port (172). In the normal operating mode, the isolation gate (192) is closed and the isolation gate (186) is opened. The transparent shift register latch (170) allows testing of interface lines between adjacent logic modules.

REFERENCES:
patent: 4428060 (1984-01-01), Blum
patent: 4503537 (1985-03-01), McAnney
patent: 4519078 (1985-05-01), Komonytsky
patent: 4575674 (1986-03-01), Bass et al.
E. J. McCluskey; "A Survey of Design for Testability Scan Techniques"; VLSI Design; Dec. 1984; pp. 36-61.

Affiliated with

Also associated with

Rating

Transparent shift register latch for isolating peripheral ports does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transparent shift register latch for isolating peripheral ports , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transparent shift register latch for isolating peripheral ports will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2119986