Minimum latency tie-breaking arbitration logic circuitry

Details Minimum latency tie-breaking arbitration logic circuitry Minimum latency tie-breaking arbitration logic circuitry

1984-10-25

1987-07-21

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 300, G06F 1300

Patent

active

046822828

ABSTRACT:
Arbitration apparatus provides first-come-first-served access for a plurality of requestors to a commonly shared unit, such as a memory. Each requestor is provided with a counter which is advanced each cycle from an initial count until its respective requestor is granted access. During each cycle, fast programmable array combinational selection logic operates in response to the counter outputs to select the requestor which has been waiting the longest. Tie-breaking combinational logic is additionally provided for resolving ties. The speed of operation of the combinational selection logic and the combinational tie-breaking logic is chosen so that requestors can be granted access at a rate of one per cycle.

REFERENCES:
patent: 3222647 (1965-12-01), Strachey
patent: 3543242 (1967-07-01), Adams, Jr. et al.
patent: 4099255 (1978-07-01), Stanley et al.
patent: 4151598 (1979-04-01), Webster
patent: 4161779 (1979-07-01), Spencer et al.

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