VLIW processing device including improved memory for avoiding co

Details VLIW processing device including improved memory for avoiding co VLIW processing device including improved memory for avoiding co

1995-04-19

1997-11-25

Robertson, David L.

395476, G06F 1338

Patent

active

056921390

ABSTRACT:
A processing device includes an imitation multiport memory circuit (10) interconnecting inputs and outputs of a group of functional units (F1, . . . FN), all operating under control of a single series of very long program instructions. The memory circuit (10) comprises a plurality of separate memory units (15), each having a read port (12) connected to a respective functional unit input, and a crossbar switching circuit (18) connected between the functional unit outputs and write ports of the separate memory units. The memory circuit (10) provides substantially the same performance as a true multiport memory but requires a smaller circuit area, allowing a larger processing device to be integrated in one chip than previously. Collisions for access to a memory unit write port can be resolved without rescheduling by use of a delay element (21,70) and/or an additional write port (82) to a memory unit.

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