System for continuous DMA transfer of virtually addressed data b

Details System for continuous DMA transfer of virtually addressed data b System for continuous DMA transfer of virtually addressed data b

1986-06-16

1989-01-10

Eng, David Y.

Boots, shoes, and leggings

G06F 1208, G06F 1300

Patent

active

047978120

ABSTRACT:
A channel apparatus including a transfer controller responsive to an input data transfer command, for translating virtual block address data designated by a channel command word (CCW) into RBA data to store the translated RBA data. The CCW commands the DMA transfer of the data over a plurality of subsequent blocks of the external memory. The translated RBA data are written in a real address storage section in a write mode. The controller outputs a transfer start instruction to a DMA transfer section after outputting an initial value of a DMA address to a DMA transfer section and writing a predetermined amount of the RBA data to the storage section. The DMA transfer section performs the DMA transfer of the data to the external memory in a read mode in accordance with the transfer start instruction while the data is being input from the external device. The transfer section generates a memory request every time performing the DMA transfer of one word of the data. At the same time, the transfer section outputs the DMA address to the storage section. In the storage section, a real address is produced in combination with the offset data in the DMA address and the stored RBA data at the read storage address in the DMA address to output the produced address to the external memory in response to the memory request.

REFERENCES:
patent: 4173783 (1979-11-01), Couleur et al.
patent: 4430701 (1984-02-01), Christian et al.
patent: 4488228 (1984-12-01), Crudele et al.

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