Method for semiconductor isolation

Details Method for semiconductor isolation Method for semiconductor isolation

1990-08-30

1993-03-09

Fourson, G.

Fishing, trapping, and vermin destroying

437228, 437944, 148DIG127, H01L 2176

Patent

active

051927063

ABSTRACT:
This is a method of forming a semiconductor integrated circuit with isolation regions, (possibly wide and narrow) comprising of a thin oxide film and deposited anisotropic oxide. It uses an inorganic layer (e.g. noncrystalline silicon) to mask what will be active areas and allows for the growth of a thermal oxide film in the trenches reducing the parasitic channel formation along the trenches. The use of anisotropic oxide to fill the trenches allows for wide and narrow trenches to be simultaneously filled to the desired depth. The removing of inorganic layer and the use of anisotropic oxide to fill the trenches produces a flat planar surface and finer isolation regions.

REFERENCES:
patent: 4444605 (1984-04-01), Slawinski
patent: 4526631 (1985-07-01), Silvestri et al.
patent: 4541167 (1985-09-01), Havemann et al.
patent: 4758531 (1988-07-01), Beyer et al.
patent: 4842675 (1989-06-01), Chapman et al.
Ehara, K., "Planar Interconnect Technology . . . Lift-Off Process", J. Electrochem. Soc.: Solid State Science & Technology, vol. 131, No. 2, Feb. 1984.
Wolf, S., Silicon Processing for the VLSI Era, vol. 1, .COPYRGT.1986, pp. 182-183, 184-187.
IBM Technical Disclosure Bulletin vol. 27, No. 12, May 1985, pp. 6981-6982.

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