Method for manufacturing semiconductor stacked CMOS devices

Details Method for manufacturing semiconductor stacked CMOS devices Method for manufacturing semiconductor stacked CMOS devices

1991-06-06

1993-03-09

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437915, 257 69, H01L 2170, H01L 2700

Patent

active

051927055

ABSTRACT:
A semiconductor stacked CMOS device in which gate electrodes are laid on the upper and lower sides of an upper MOS FET, and a gate oxide film of the upper MOS FET is formed by oxidizing polycrystalline Si film having a low impurity concentration, wherey the current drive capability and the insulative proof-voltage can be enhanced. Further, the polycrystalline Si is formed on a silicon nitride film or a silicon oxide film having a less surface roughness, and accordingly, the lower surface of the polycrystalline Si has also a less surface roughness, whereby it is possible to further enhance the insulative proof-voltage.

REFERENCES:
patent: 4502202 (1985-03-01), Malhi
patent: 4555721 (1985-11-01), Bansal et al.
patent: 4628589 (1986-12-01), Sundaresan
patent: 4651408 (1987-03-01), MacElwee et al.
patent: 4656731 (1987-04-01), Lam et al.
patent: 4698659 (1987-10-01), Mizutani
patent: 4997785 (1991-03-01), Pfiester
"Process and Performances comparison of an 8K x 8-bit SCRAM in Three Stacked CMOS Technologies" from IEEE Electron Device Letters, vol. EDL-6 No. 10. Oct. 1985.

Affiliated with

Also associated with

Rating

Method for manufacturing semiconductor stacked CMOS devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing semiconductor stacked CMOS devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor stacked CMOS devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-211123