Self-aligned silicon MOS device

Details Self-aligned silicon MOS device Self-aligned silicon MOS device

1987-09-14

1989-01-10

James, Andrew J.

357 56, 357 59, 357 237, 357 239, H01L 2978

Patent

active

047977183

ABSTRACT:
An MOS transistor having relatively low parasitic capacitances is achieved by forming a dielectrically isolated mesa on a monocrystalline substrate. Such mesa includes a polycrystalline silicon region that serves as a gate region and an oxide layer that serves as a gate oxide. Subsequently, such mesa is made to sit on a platform, arising from the silicon substrate and surrounded by a sea of silicon dioxide originally at the level of the bottom of the mesa. The level of this sea is lowered to expose opposed sides of the platform to which is grown separate regions of lateral epitaxial silicon that serve as the source and drain of the transistor.

REFERENCES:
patent: Re31580 (1984-05-01), Kooi
patent: 3544858 (1970-12-01), Kooi
patent: 3958040 (1976-05-01), Webb
patent: 4178197 (1979-12-01), Marinace
patent: 4333965 (1982-06-01), Chow et al.
patent: 4384301 (1983-05-01), Tasch, Jr. et al.
patent: 4428111 (1984-01-01), Swartz
patent: 4522682 (1985-06-01), Soclof
patent: 4533431 (1985-08-01), Dargent

Affiliated with

Also associated with

Rating

Self-aligned silicon MOS device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned silicon MOS device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned silicon MOS device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2110748