Floating gate memory process with improved dielectric

Details Floating gate memory process with improved dielectric Floating gate memory process with improved dielectric

1986-05-27

1987-10-06

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 43, H01L 21425

Patent

active

046973303

ABSTRACT:
The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide
itride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

REFERENCES:
patent: 4409723 (1983-10-01), Harari
patent: 4451904 (1984-05-01), Suguira et al.
patent: 4456978 (1984-06-01), Morley et al.
patent: 4495693 (1985-01-01), Iwahashi et al.
patent: 4532022 (1985-07-01), Takasaki et al.
patent: 4581622 (1986-04-01), Takasaki et al.
patent: 4630086 (1986-12-01), Sato et al.

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