Prefetching into a cache to minimize main memory access time and

Details Prefetching into a cache to minimize main memory access time and Prefetching into a cache to minimize main memory access time and

1994-11-15

1996-03-12

Swann, Tod R.

Boots, shoes, and leggings

395414, 395445, 395450, 3642631, 364948, 36424341, 36496422, 36496423, 36496424, 364DIG1, 364DIG2, G06F 1300

Patent

active

054993555

ABSTRACT:
A cache subsystem for a computer system having a processor and a main memory is described. The cache subsystem includes a prefetch buffer coupled to the processor and the main memory. The prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor. The predicted address is based upon an address for a last memory fetch from the processor. A main cache is coupled to the processor and the main memory. The main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer. The main cache stores a second data fetched from the main memory in accordance with the address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address. The address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.

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