Pipelined data processor which conditionally executes a predeter

Details Pipelined data processor which conditionally executes a predeter Pipelined data processor which conditionally executes a predeter

1991-03-27

1994-04-12

Lall, Parshotam S.

Boots, shoes, and leggings

364262, 3642624, 364DIG1, G06F 900, G06F 940

Patent

active

053033558

ABSTRACT:
A data processor (10) having an instruction fetch unit (12), a decode and control unit (14), and an execution unit 16 performs conditionally executed instructions in hardware. A conditional break instruction, BRKcc, is inserted within a looping instruction to conditionally terminate the looping instruction with a minimum number of instruction cycles. A conditional do-loop instruction, DO#0, prevents the data processor (10) from executing a do-loop with a loop count within a loop counter (24) of zero upon entry. A conditional repeat instruction, REP#0, prevents a repeat instruction from being executed if a loop count is zero upon entry. A conditional repeat instruction, REPcc, allows a subsequent instruction to be conditionally terminated during execution.

REFERENCES:
patent: 4652997 (1987-03-01), Kolker
patent: 4727483 (1988-02-01), Saxe
patent: 4882701 (1989-11-01), Ishii
patent: 5051896 (1991-09-01), Lee et al.
patent: 5101484 (1992-03-01), Kohn
Motorola DSP56116 Digital Signal Processor User's Manual, Oct. 1990, pp. A-50, A-51, A-80-A-89, A-178-A-183.
Proceedings ICASSP 90, 1990 International Conference On Acoustics, Speech, and Signal Processing, Apr. 3-6, 1990, IEEE Signal Processing Society.
Nov. 5, 1990 Press Release Statements from Motorola, Inc., Spectrum Signal Processing, Inc., Ariel Corporation, and Mentor Graphics.

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