Semiconductor structure for long-term learning

Details Semiconductor structure for long-term learning Semiconductor structure for long-term learning

1998-11-30

2000-09-26

Hoang, Huan

Static information storage and retrieval

Floating gate

Multiple values

36518528, 257315, G11C 1604

Patent

active

061250538

ABSTRACT:
A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.

REFERENCES:
patent: 5864242 (1999-06-01), Allen et al.
patent: 5914894 (1999-06-01), Diorio et al.

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