Timer circuit

Details Timer circuit Timer circuit

1993-02-04

1994-04-12

Sikes, William L.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Including structure for detecting or indicating overflow...

377 56, 307603, H03K 2108

Patent

active

053032799

ABSTRACT:
An n-bit input count value is split into high-order n-1 bits and a low-order one bit so that the overflow signal 3a of the n-1 bit counter 2 for counting the high-order n-1 bits and the output signal 4a which is obtained by delaying the overflow signal 3a by half the cycle of the input clock by means of the delay circuit 4 are switched by the switch circuit 5 according to the low-order bit stored in the 1-bit register 6 to achieve a signal having a minimum decomposition width which is half the cycle of the input clock 7a.

REFERENCES:
patent: 3890490 (1975-06-01), Bnenger
patent: 4413350 (1983-11-01), Bond et al.
patent: 4584494 (1986-04-01), Arakawa et al.
patent: 4713832 (1987-12-01), Hutson
M37702M2-XXXFB Single-Chip 16-Bit CMOS Microcomputer Databook, Mitsubishi Electric, pp. 2-22, 2-23.

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