Logic elements for interlaced carry/borrow systems having a unif

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364787, G06F 750

Patent

active

054992036

ABSTRACT:
Logic elements for use in carry/borrow and comparator systems, which operate in accordance with the IMPLY logical relationship. Utilization of the IMPLY logical relationship overcomes the inherent complication of inversion so that it becomes an effective benefit, making possible uniform carry system layouts with uniform logic elements using a newly defined gate pair combination in general. The gate pair logic elements provide a novel carry-propagate signal (P) which includes a redundant carry-generate signal (G), thereby defining a novel carry-integrate signal (I) . The novel carry-integrate, signal (I) together with the carry-generate signal (G) define a signal pair utilized in succeeding carry levels which are organized in a simplified fashion. For-2-bit position (i+1, i) positive sense logic, the carry-integrate signal can be represented by I(i+1, i)=G(i+1)+P(i+1). P(i)) . Wherever the IMPLY relationship is involved in logic functions, the design of CMOS gates is affected and can be modified. The novelty is characterized in the embodiment of gates featuring Symmetrical structure of switching pairs and crosswise (Anti-Symmetrical) wiring actuating these pairs (SAS gates), where pairs of gates are not fed by a common input signal, rather they are fed by a pair of signals having the IMPLY relationship. This leads to a special family of gates which are useful for the design of carry systems and are also independently adaptable for other specific logic functions including gates having the Tri-State feature, such as bit-sum cells and an arithmetic ZERO detection circuit.

REFERENCES:
patent: 4882698 (1989-11-01), Young
patent: 5043934 (1991-08-01), Lamb
patent: 5235539 (1993-08-01), Patel

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