High performance array multiplier using four-to-two composite co

Details High performance array multiplier using four-to-two composite co High performance array multiplier using four-to-two composite co

1992-07-20

1994-04-12

Nguyen, Long T.

Boots, shoes, and leggings

G06F 752

Patent

active

053031768

ABSTRACT:
An apparatus for the reduction of partial products of a multiplier combines attributes of pre-addition and the regularity found in array multipliers by employing improved four-to-two composite counter cells. This composite counter cell, the basic block for reducing the partial products, is itself comprised of two new four-to-two counters. One of the four-to-two counters is used to perform pre-addition of the partial products while the second counter is used to perform addition between the sum produced by the counter performing the pre-addition and the outputs from the second counter of a cell in a previous stage of the addition. The regularity of array multiplication schemes is preserved and interconnections required by the mechanism span no more than two columns of the matrix.

REFERENCES:
patent: 4228520 (1980-10-01), Letteney et al.
patent: 4752905 (1988-06-01), Nakagawa et al.
patent: 4769780 (1988-09-01), Chang
patent: 4926371 (1990-05-01), Vassiliadis et al.
patent: 5072419 (1991-12-01), Zyner
patent: 5101372 (1992-03-01), Heaslip

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