Boots – shoes – and leggings
Patent
1993-07-29
1994-04-12
Mai, Tan V.
Boots, shoes, and leggings
364745, G06F 738
Patent
active
053031750
ABSTRACT:
The number of zeroes in an operation result of 54 bits is counted by a priority encoder 2 on a three-bit basis. A 54.times.18 normalization shifter 3 normalizes the operation result in response to the counted result. An LSB determination logic 4 determines a position of the LSB shifted by overflow and underflow, according to a logic state of the most significant three bits of the operation result, and an increment signal generating portion 5 and a three-bit input incrementer 6 add 1 corresponding to the shifted LSB to generate a round-up signal. A 54.times.3 normalization shifter 9 selectively normalizes a processed result of a lost-significant bit processing portion B or that of a round processing portion A. Normalization shifters of the lost-significant bit processing portion constitute a two stage structure, in which the normalization shifter in the final stage also serves for the rounding processing portion, and a normalization shifter in the succeeding stage of an arithmetic operation portion is omitted. Consequently, a floating point arithmetic unit with the reduced volume of hardware can be provided without reducing the operation speed.
REFERENCES:
patent: 4954978 (1990-09-01), Terane et al.
patent: 5257215 (1993-10-01), Poon
Computer Architecture: A Quantitative Approach, by David A. Patterson, et al, pp. A18-A19, 1990.
Mai Tan V.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Floating point arithmetic unit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Floating point arithmetic unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating point arithmetic unit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2104421