Method for VLSI layout pattern compaction by using direct access

Details Method for VLSI layout pattern compaction by using direct access Method for VLSI layout pattern compaction by using direct access

1991-04-17

1993-11-30

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

052671771

ABSTRACT:
A method for layout compaction which comprises steps of establishing storage areas in a direct access memory as a boundary information memory to which geometrical information on boundaries of a layout is written, searching layout elements of groups adjoining the boundaries of the layout and performing a processing of packing layout elements in a bottom boundary region of the layout and of packing layout elements in a top boundary region of the layout by using the boundary information memory. Thereby, a compaction of the layout can be performed at a high speed.

REFERENCES:
patent: 4500963 (1985-02-01), Smith et al.
patent: 4965739 (1990-10-01), Ng
patent: 5079717 (1992-01-01), Miwa
"A Hierarchical Routing System for VLSIs Including Large Macros" by Hiwatashi et al., IEEE 1986 Cust. Integrated Circuits Conf., pp. 235-238.
"An Over-All Gate Array Channel Router" by Krohn, IEEE 20th Design Automation Conf., 1983, pp. 665-670.
"Compaction Based Custom LSI Layout Design Method" by Ishikawa et al., IEEE International Conference on Computer-Aided Design, Nov. 1985, pp. 343-345.
Xiao-Ming Xiong and Ernest S. Kuh, "Nutcracker: An Efficient and Intelligent Channel Spacer" 24th ACM/IEEE Digest Automation Conference, Paper 17.2, 1987, pp. 298-304.

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