Input circuit block and method for PLDs with register clock enab

Details Input circuit block and method for PLDs with register clock enab Input circuit block and method for PLDs with register clock enab

1993-03-18

1994-04-12

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072722, 307475, 307480, H03K 3289

Patent

active

053028660

ABSTRACT:
An input block for PLDs programmable logic devices) has a flip-flop including a master latch and a slave latch, a pad for inputting data, configuration bits, and a global clock input signal for clocking the input data to the flip-flop means. The flip-flop is controlled by the configuration bits so as to function alternatively as a register, a latch or transparently. The input block further includes at least one clock enable signal input terminal and logic elements responding to the configuration bits for providing the clock enable signal for the register function as well as the latch function of the flip-flop.

REFERENCES:
patent: 4942318 (1990-07-01), Kawana
patent: 4992679 (1991-02-01), Takata et al.
patent: 5023484 (1991-06-01), Pathak et al.
patent: 5198705 (1993-03-01), Galbraith et al.

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