Interlaced CCD memory

Details Interlaced CCD memory Interlaced CCD memory

1977-12-30

1978-09-26

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365183, 307238, G11C 1140

Patent

active

041175468

ABSTRACT:
Disclosed is an interlaced serial-parallel-serial (SPS) charge coupled device (CCD) memory with improved clocking. By performing the interlacing as well as the serial-parallel-serial function with only seven clock pulses, less metallurgy and consequently less space per bit on a semiconductor chip is required. By reducing the number of clock requirements, the supporting logic circuitry is simplified permitting a larger portion of the semiconductor chip area to be used for data bit storage.

REFERENCES:
patent: 3763480 (1973-08-01), Weimer

Affiliated with

Also associated with

Rating

Interlaced CCD memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interlaced CCD memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interlaced CCD memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2094259