Method of manufacturing semiconductor device with reduced packag

Details Method of manufacturing semiconductor device with reduced packag Method of manufacturing semiconductor device with reduced packag

1991-06-03

1992-12-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437219, 148DIG103, H01L 2156, H01L 2160

Patent

active

051717166

ABSTRACT:
A semiconductor device contains a stress-relief layer (46) having a glass transition temperature below 150.degree. C. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer is preferably made by lithographic patterning.

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